Integration and Design of High-Speed RISC-V Cores for Scalable Architectures

Karthik Wali

doi:10.70528/IJLRP.v5.i1.1622

Integration and Design of High-Speed RISC-V Cores for Scalable Architectures

Author(s)	Karthik Wali
Country	United States
Abstract	The explosive growth in data-driven applications—spanning from machine learning inference at the edge to high-performance computing in data centers—has fueled the need for application-specific, high-speed processor cores. The open and extensible RISC-V instruction set architecture (ISA) provides a compelling platform for such processors. This paper describes an end-to-end approach to designing and integrating high-speed RISC-V cores optimized for scalable computing architectures. We outline a sophisticated core microarchitecture that uses deep pipelining, dynamic branch prediction, and superscalar instruction issue to increase instruction throughput. Additionally, the cores are architected to support coherent multi-level cache hierarchies for effortless integration into multiple-core systems. To ensure our methodology, we utilized a hybrid approach consisting of Register-Transfer Level (RTL) modeling, FPGA prototyping, and cycle-accurate simulation with tools like Gem5 and Vivado. Our foundation was synthesized and tested on a Xilinx UltraScale+ FPGA, where it recorded a clock frequency of over 1.2 GHz and showed a 25% gain in performance-per-watt over state-of-the-art open-source RISC-V cores. We also designed a scalable interconnect fabric using a mesh Network-on-Chip (NoC) to enable effective communication between multiple cores with low latency and coherence across the memory subsystem. The experimental findings reinforce the efficiency of our design to provide high performance and energy savings without compromising on scalability. The results present seminal insights into architecting trade-offs in building high-speed RISC-V cores and set the foundation for further study of domain-specific accelerators, chiplet-level integration, and heterogeneous computing landscapes based on RISC-V. This research will contribute to the expanding universe of open hardware innovation and facilitate the creation of next-generation processing platforms that are not only high-performance but also transparent, flexible, and economical.
Field	Engineering
Published In	Volume 5, Issue 1, January 2024
Published On	2024-01-06
Cite This	Integration and Design of High-Speed RISC-V Cores for Scalable Architectures - Karthik Wali - IJLRP Volume 5, Issue 1, January 2024. DOI 10.70528/IJLRP.v5.i1.1622
DOI	https://doi.org/10.70528/IJLRP.v5.i1.1622
Short DOI	https://doi.org/g9q4d7

View / Download PDF File

doi

CrossRef DOI is assigned to each research paper published in our journal.

IJLRP DOI prefix is
10.70528/IJLRP

Downloads

Research Paper Format Copyright Permission Form and Undertaking Form Cover Page Vol 6 Isu 7 Cover Page Vol 6 Isu 6 Cover Page Vol 6 Isu 5

All research papers published on this website are licensed under Creative Commons Attribution-ShareAlike 4.0 International License, and all rights belong to their respective authors/researchers.

CC-BY-SA

About IJLRP Fees & Payment Current Issue Publication Archive	Submit Research Paper Track Submission Status Publication Guidelines Publication Ethics Peer Review & Plagiarism	Join as a Reviewer Editors & Reviewers Reviewer Referral Program Get Reviewer Membership Certi.	Website/Journal Policies Usage Policy Content Policies Privacy Policy

Contact Us		+91-9687-828-838	editor@ijlrp.com

International Journal of Leading Research Publication

A Widely Indexed Open Access Peer Reviewed Multidisciplinary Bi-monthly Scholarly International Journal

Integration and Design of High-Speed RISC-V Cores for Scalable Architectures

Share this